基于Xilinx FPGA的DDR3控制器读写程序，此程序已经用于实际的项目中，读写控制很稳定。上传的是一个实际的DDR3工程，开发环境为Vivado 2017.4
代码片段和文件信息
属性 大小 日期 时间 名称
----------- --------- ---------- ----- ----
目录 0 2018-04-15 18:56 DDR_ctrl
目录 0 2018-04-15 18:56 DDR_ctrlproject_1
目录 0 2018-04-14 14:24 DDR_ctrlproject_1project_1.cache
目录 0 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip
目录 0 2018-04-14 16:08 DDR_ctrlproject_1project_1.cacheip2017.4
目录 0 2018-04-14 15:22 DDR_ctrlproject_1project_1.cacheip2017.45bc081bc6e4900f7
文件 7366 2018-04-14 15:22 DDR_ctrlproject_1project_1.cacheip2017.45bc081bc6e4900f75bc081bc6e4900f7.xci
文件 330469 2018-04-14 15:22 DDR_ctrlproject_1project_1.cacheip2017.45bc081bc6e4900f7dbg_hub_CV.dcp
目录 0 2018-04-14 15:26 DDR_ctrlproject_1project_1.cacheip2017.46c7a431b889965ad
文件 398343 2018-04-14 15:26 DDR_ctrlproject_1project_1.cacheip2017.46c7a431b889965ad6c7a431b889965ad.xci
文件 1785006 2018-04-14 15:26 DDR_ctrlproject_1project_1.cacheip2017.46c7a431b889965adu_ila_0_CV.dcp
目录 0 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c
目录 0 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c.logs
文件 21535 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c.logs
unme.log
文件 37485 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c8530466f3faacb1c.xci
文件 9169 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0.dcp
文件 7233 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_sim_netlist.v
文件 7220 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_sim_netlist.vhdl
文件 1276 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_stub.v
文件 1308 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_stub.vhdl
目录 0 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691
目录 0 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691.logs
文件 20497 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691.logs
unme.log
文件 37475 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c6918706cdeb4165c691.xci
文件 8712 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0.dcp
文件 5649 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_sim_netlist.v
文件 5497 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_sim_netlist.vhdl
文件 1276 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_stub.v
文件 1308 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_stub.vhdl
目录 0 2018-04-14 14:31 DDR_ctrlproject_1project_1.cacheip2017.417879824c91b8b0
目录 0 2018-04-14 14:31 DDR_ctrlproject_1project_1.cacheip2017.417879824c91b8b0.logs
............此处省略487个文件信息
----------- --------- ---------- ----- ----
目录 0 2018-04-15 18:56 DDR_ctrl
目录 0 2018-04-15 18:56 DDR_ctrlproject_1
目录 0 2018-04-14 14:24 DDR_ctrlproject_1project_1.cache
目录 0 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip
目录 0 2018-04-14 16:08 DDR_ctrlproject_1project_1.cacheip2017.4
目录 0 2018-04-14 15:22 DDR_ctrlproject_1project_1.cacheip2017.45bc081bc6e4900f7
文件 7366 2018-04-14 15:22 DDR_ctrlproject_1project_1.cacheip2017.45bc081bc6e4900f75bc081bc6e4900f7.xci
文件 330469 2018-04-14 15:22 DDR_ctrlproject_1project_1.cacheip2017.45bc081bc6e4900f7dbg_hub_CV.dcp
目录 0 2018-04-14 15:26 DDR_ctrlproject_1project_1.cacheip2017.46c7a431b889965ad
文件 398343 2018-04-14 15:26 DDR_ctrlproject_1project_1.cacheip2017.46c7a431b889965ad6c7a431b889965ad.xci
文件 1785006 2018-04-14 15:26 DDR_ctrlproject_1project_1.cacheip2017.46c7a431b889965adu_ila_0_CV.dcp
目录 0 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c
目录 0 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c.logs
文件 21535 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c.logs
unme.log
文件 37485 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1c8530466f3faacb1c.xci
文件 9169 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0.dcp
文件 7233 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_sim_netlist.v
文件 7220 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_sim_netlist.vhdl
文件 1276 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_stub.v
文件 1308 2018-04-14 14:57 DDR_ctrlproject_1project_1.cacheip2017.48530466f3faacb1cclk_wiz_0_stub.vhdl
目录 0 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691
目录 0 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691.logs
文件 20497 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691.logs
unme.log
文件 37475 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c6918706cdeb4165c691.xci
文件 8712 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0.dcp
文件 5649 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_sim_netlist.v
文件 5497 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_sim_netlist.vhdl
文件 1276 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_stub.v
文件 1308 2018-04-14 15:35 DDR_ctrlproject_1project_1.cacheip2017.48706cdeb4165c691clk_wiz_0_stub.vhdl
目录 0 2018-04-14 14:31 DDR_ctrlproject_1project_1.cacheip2017.417879824c91b8b0
目录 0 2018-04-14 14:31 DDR_ctrlproject_1project_1.cacheip2017.417879824c91b8b0.logs
............此处省略487个文件信息
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